Data Sheet
ADP2140
Rev. A | Page 5 of 32
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
VIN1, VIN2 to PGND, AGND
0.3 V to +6.5 V
VOUT2 to PGND, AGND
0.3 V to V
IN2
SW to PGND, AGND
0.3 V to V
FB to PGND, AGND
0.3 V to +6.5 V
PG to PGND, AGND
0.3 V to +6.5 V
EN1, EN2 to PGND, AGND
0.3 V to +6.5 V
Storage Temperature Range
65癈 to +150癈
Operating Ambient Temperature Range
40癈 to +85癈
Operating Junction Temperature Range
40癈 to +125癈
Soldering Conditions
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in com-
bination. The ADP2140 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that T
J
is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (T
J
) of the device is dependent on the
ambient temperature (T
A
), the power dissipation of the device
(P
D
), and the junction-to-ambient thermal resistance of the
package (?/DIV>
JA
).
Maximum junction temperature (T
J
) is calculated from the
ambient temperature (T
A
) and power dissipation (P
D
) using the
formula
T
J
= T
A
+ (P
D
??/DIV>
JA
)
Junction-to-ambient thermal resistance (?/DIV>
JA
) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of ?/DIV>
JA
may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of ?/DIV>
JA
are based on a 4-layer, 4 in. ?3 in. circuit
board. Refer to JESD 51-7 for detailed information on the board
construction.
For more information, see AN-772 Application Note, A Design
and Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
?/DIV>
JB
is the junction-to-board thermal characterization parameter
with units of 癈/W. ?/DIV>
JB
of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. ?/DIV>
JB
measures the component power flowing through
multiple thermal paths rather than a single path, as in thermal
resistance, ?/DIV>
JB
. Therefore, ?/DIV>
JB
thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make ?/DIV>
JB
more useful in real-world applications.
Maximum junction temperature (T
J
) is calculated from the
board temperature (T
B
) and power dissipation (P
D
) using the
formula
T
J
= T
B
+ (P
D
??/DIV>
JB
)
Refer to JESD51-8 and JESD51-12 for more detailed
information about ?/DIV>
JB
.
THERMAL RESISTANCE
?/DIV>
JA
and ?/DIV>
JB
are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
?/DIV>
A
?nbsp
Unit
10-Lead 3 mm ?3 mm LFCSP
35.3
16.9 癈/W
ESD CAUTION
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